extern void alt_itlb (VCPU *vcpu, u64 vadr);
extern void itlb_fault (VCPU *vcpu, u64 vadr);
extern void ivhpt_fault (VCPU *vcpu, u64 vadr);
+extern unsigned long handle_fpu_swa (int fp_fault, struct pt_regs *regs, unsigned long isr);
#define DOMN_PAL_REQUEST 0x110000
#define DOMN_SAL_REQUEST 0x110001
VCPU *vcpu = current;
UINT64 vpsr = vmx_vcpu_get_psr(vcpu);
vector=vec2off[vector];
- if(!(vpsr&IA64_PSR_IC)&&(vector!=0x1400)){
+ if(!(vpsr&IA64_PSR_IC)&&(vector!=IA64_DATA_NESTED_TLB_VECTOR)){
panic_domain(regs, "Guest nested fault vector=%lx!\n", vector);
}
+ else{ // handle fpswa emulation
+ // fp fault
+ if(vector == IA64_FP_FAULT_VECTOR && !handle_fpu_swa(1, regs, isr)){
+ vmx_vcpu_increment_iip(vcpu);
+ return;
+ }
+ //fp trap
+ else if(vector == IA64_FP_TRAP_VECTOR && !handle_fpu_swa(0, regs, isr)){
+ return;
+ }
+ }
VCPU(vcpu,isr)=isr;
VCPU(vcpu,iipa) = regs->cr_iip;
if (vector == IA64_BREAK_VECTOR || vector == IA64_SPECULATION_VECTOR)
/*
* Handle floating-point assist faults and traps for domain.
*/
-static unsigned long
+unsigned long
handle_fpu_swa (int fp_fault, struct pt_regs *regs, unsigned long isr)
{
struct vcpu *v = current;
PSCBX(v, fpswa_ret) = ret;
printk("%s(%s): fp_emulate() returned %ld\n",
__FUNCTION__, fp_fault?"fault":"trap", ret.status);
- } else {
- if (fp_fault) {
- /* emulation was successful */
- vcpu_increment_iip(v);
- }
}
return ret.status;
// FIXME: Should we handle unaligned refs in Xen??
vector = IA64_UNALIGNED_REF_VECTOR; break;
case 32:
- if (!(handle_fpu_swa(1, regs, isr))) return;
+ if (!(handle_fpu_swa(1, regs, isr))) {
+ vcpu_increment_iip(v);
+ return;
+ }
printf("ia64_handle_reflection: handling FP fault\n");
vector = IA64_FP_FAULT_VECTOR; break;
case 33: